College of Engineering and Computer Science

In this informative and exciting Conference & Exhibit, learn from experts in many leading-edge companies, academia, and organizations driving the latest System-on-Chip (SoC), ASIC, and Foundry technologies.

Participating Companies & Organizations (a partial list): IBM, Toshiba, NEC, Samsung, Cadence, Tensilica, eASIC, Micron Technology, Denali, Philips, Altera, ARM, Giga Scale IC, Fujitsu, Texas Instruments, Synplicity, CEVA-DSP, Georgia Institute of Technology , LSI Logic, SMT, UCI, Elixent, iSuppli, RapidIO, Magma, Nascentric, Synfora, EETimes, Aplus Flash Technology, Taylor & Francis - CRC Press, Chartered Semiconductor, SJS University, OCP-IP, MoSys, EDACafe, BlueRISC, Circuit Cellar, Virage Logic, DSP & FPGA, CSU Fullerton, Adaptive Labs, CSU Long Beach, AeA, Electronic Design, Savant Company Inc., Advanced Packaging, Si2, Palmchip, Semiconductor Online , Embedded Computing , Chapman University, Chip Design , Open Systems Initiatives, Extension Media, OCBC, Minova, IEEE OC, VSIA Alliance, Kilopass, Jazz Semiconductor, and many more.

Four Informative Tracks

	CPUs & DSPs for SoC/ASIC Applications
	Memory Subsystem for System-on-Chip (SoC/ASIC) Designs
	New Trends and Approaches in SoC and ASIC Designs
	EDA Tools and Methodologies for 65nm and Beyond

Four Outstanding Keynote Speakers

	Jon Kang-Senior VP, Samsung Semiconductor
	Derek Lidow-CEO and President, iSuppli
	Dr. Rao Tummala-Georgia Institute of Technology
	Dr. Juan-Antonio Carballo-IBM

Two Enlightening Panels

	Memory Subsystem for System-on-Chip Designs. Moderator: Dave Bursky, Electronic Design Magazine
	Myth or Reality: Power Reduction at All levels of Design Abstraction. Moderator: Ron Wilson, EETimes

One Night of Tabletop Exhibitions (November 1, 2005, 4:30PM - 8:30PM)

	Sign up online for c omplimentary exhibition passes (for November 1, 2005, Exhibition night only).
	Meet one-on-one with SoC experts representing a wide variety of companies
	Have your toughest questions answered by leading-edge companies!
	Discuss development tools and chip design challenges with SoC/ASIC/Foundry experts
	Connect with companies offering practical solutions to your design challenges
	"Seeing Is Believing!" See demos of EDA tools from leading-edge EDA vendors

Why You Should Attend

	Discuss 65nm and post-65nm challenges for SoC/ASIC/ASSP/FPGA designs
	Learn about the latest configurable CPUs, Processors, and DSPs cores
	Gain insight into memory subsystems design for complex SoC/ASIC/ASSP/FPGA designs
	Learn about the new trends and future direction of System-on-Chip
	Network with the leaders driving SoC technology during the conference & exhibit
	Learn about the latest EDA Tools and design techniques for Nanometer SoCs

Who Should Attend

	Chip designers
	Design engineers
	ASIC/SoC/ASSP/FPGA designers
	System architects
	System platform designers
	Executives and business decision-makers in technology companies
	Technical marketing/sales professionals
	Technology and business analysts
	Engineering professors and students
	Anyone involved with ASIC, SoC, ASSP, Foundry, and FPGA design, development, planning, promotion, and procurement

In less than two years, Savant's International System-on-Chip (SoC) Conferences & Exhibit s have become one of the most important technical and informative conferences for the chip design community. Savant conferences are recognized for their highly practical, educational content and for their collaboration with major industry enablers and top academic experts.

The Most Targeted & Informative System-on-Chip Conference & Exhibit Event of the Year

Don't Miss Out!

Register Today and Save $150! www.SoCconference.com